1. Field of the Invention
Exemplary embodiments of the present invention relate to semiconductor devices and methods of manufacturing such semiconductor devices. More particularly, exemplary embodiments of the present invention relate to semiconductor devices formed on a strained silicon layer and methods of manufacturing such semiconductor devices.
2. Description of the Related Art
Recently, semiconductor devices have experienced rapid development as information media, such as computers, have become widespread. Semiconductor devices that operate with a high response speed and a large storage capacity are in demand. In order to meet these requirements, the manufacturing technology for fabricating semiconductor devices has been developed to improve integration degree, reliability, response speed, etc.
A transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), is well known as one of the principal semiconductor devices. A current transistor may be operated with a high response speed at a low voltage, and the technology for manufacturing such a transistor has developed to improve an integration degree of such a transistor and to reduce a size dimension of such a transistor.
To obtain a transistor of a high response speed, a transistor having a channel region formed in a strained silicon layer of the transistor has been developed. Such a transistor may have an enhanced mobility of electrons or holes. The term “strained silicon layer” as used herein means a silicon layer in which a normal bonding distance between silicon atoms comprising such layer may be either extended or compressed in accordance with a lattice parameter of an underlayer positioned beneath the silicon layer. When a channel is formed in such a tensile-strained silicon layer, mobility of electrons or holes may be improved so that a P-type metal oxide semiconductor (PMOS) or an N-type metal oxide semiconductor (NMOS) may be advantageously formed on the tensile-strained silicon layer. Thus, the use of a strained silicon layer has been widely researched as one technique to obtain a transistor having a high response speed. This strained silicon layer may be formed through various methods.
In one method for forming a strained silicon layer, the strained silicon layer may be formed by adjusting a stress generated therein. For example, a strained silicon layer can be formed using a tensile stress generated in an interface between a silicon substrate and a nitrate layer formed on the silicon substrate.
According to another method for forming a strained silicon layer, the strained silicon layer may be grown on a silicon germanium layer after the silicon germanium layer is formed on a semiconductor substrate. Because the strained silicon layer is grown on the silicon germanium layer, which has a lattice parameter that is relatively larger, the bonding distance between silicon atoms in the strained silicon layer may be larger than between silicon atoms of a conventional single crystalline silicon layer. Here, lattice mismatches of the silicon germanium layer may be increased in accordance with an increase in the content of germanium in the silicon germanium layer, so that the bonding distance between the silicon atoms in the strained silicon layer may be further increased by increasing the germanium content of the silicon germanium layer.
When a strained silicon layer having a relatively greater thickness is formed on a silicon germanium layer having a relatively high content of germanium, a stress in the strained silicon layer may be considerably increased. In fact, in some instances where the stress in a strained silicon layer is increased to beyond a certain limiting point, a strain relaxation may subsequently occur in the strained silicon layer as a result of a crystalline structure of the strained silicon layer being broken. Also, when the content of germanium of the silicon germanium layer is about 30 percent by weight based on the total weight of the silicon germanium layer, the strained silicon layer may be grown on the silicon germanium layer to a relatively great thickness ranging from several tens angstroms to as much as several hundreds of angstroms. In such cases, an isolation layer or source/drain regions of a transistor should be extended completely through the strained silicon layer to the silicon germanium layer.
Since the silicon germanium layer has different characteristics from those of the strained silicon layer relative to an etching process, a cleaning process, a diffusion process, etc., a failure of the transistor may easily occur in the course of forming an isolation layer or the source/drain regions. Additionally, the aforementioned fabrication processes may be complicated because those processes should normally be carried out taking into account the etching, cleaning and diffusion characteristics of the silicon germanium layer and the strained silicon layer while forming the isolation layer and/or the source/drain regions.
As the lattice mismatches of the silicon germanium layer are increased, the stress in the strained silicon may be also augmented, and thus defects in the strained silicon layer may be increased. When the defects of the strained silicon layer are thus augmented, a leakage current from the transistor may be increased and reliability of the transistor may thereby be lowered.
Some methods of forming transistors on strained silicon layers are disclosed in Japanese Laid-Open Patent Publications No. 2002-094060 and No. 2000-031491, which disclosures are incorporated herein by reference. In a method of the Japanese Laid-Open Patent Publication No. 2002-094060, a transistor is formed on a strained silicon layer positioned on a silicon germanium layer after an isolation layer and a well region are formed in the silicon germanium layer. Because an etching rate of the silicon germanium layer may be very high when the silicon germanium layer has lattice defects, the isolation layer may not be properly formed due to a difficulty in performing uniform etching of the silicon germanium layer. Further, an impurity concentration of the well region may not be properly adjusted because impurities may be rapidly diffused into the silicon germanium layer during an ion implantation process for forming the well region.
A transistor according to Japanese Laid-Open Patent Publication No. 2000-031491 has an isolation layer extending to a buried oxide layer (BOX) in a substrate. However, an etching process for forming the isolation layer may not be easily performed when the isolation layer extends to the BOX in the substrate. That is, a strained silicon layer, and a silicon germanium layer beneath the strained silicon layer, are typically etched together during the etching process for forming the isolation layer, so that the etching process may be complicated, and a trench for the isolation layer may not have a desired profile. Additionally, adjacent transistors are completely separated from each other such that a semiconductor device including such adjacent transistors may be deteriorated by self-heating of the transistors during an operation used in fabricating the semiconductor device.
These and other problems with and limitations of the prior art techniques are addressed in whole, or at least in part, by the devices and methods of this invention.